For flip-chip, multi-layer IC devices, debugging for defects in the IC is difficult due to having to approach the desired layers from the backside of the device. FIG. 1 illustrates a sideview block diagram of a typical flip-chip configuration. As shown in FIG. 1, an IC device 10 is coupled to a ceramic package 12 (e.g., a C4 package) via solder bumps 14. The solder bumps 14 act as chip-to-carrier interconnects to attach the IC device 10 to the ceramic package 12 and to mate with corresponding pad patterns to form the necessary electrical contacts between the circuit(s) of the IC device 10 and pins of the package 12.
Device analysis remains a challenge due to the upside-down nature of the flip-chip orientation. Thus, device deprocessing of flip-chip oriented IC devices faces several difficulties. Normal deprocessing utilizes mechanical polishing of the thick silicon backside layer in order to more readily access the circuit features at the frontside layers. The mechanical polishing used from the backside removes the silicon and creates a very thin device. The reduced thickness allows utilization of an infrared (IR) optical device to view the device. A support structure typically holds the device during the thinning process. Once thinned, the device then requires removal from the support before the deprocessing procedure continues. Unfortunately, the thin device created by polishing is difficult to handle and subsequently utilize in further device analysis, which normally requires multiple steps for the removal of the device from the support to perform well-established delayering techniques from a frontside of the device. Breakage of the device often occurs due to the thinness of the device and brittleness of the silicon. Thus, the process is highly problematic and significantly time-consuming.
Accordingly, a need exists for a technique that reduces the risk of breakage when handling thinned dies. The present invention addresses such a need.